1. Field of the Invention
The present invention relates to a tuning method of process parameters of a memory and more particularly, to a tuning method of minimizing operating voltage for a static random access memory.
2. Description of Related Art
The Static Random Access Memory (SRAM) is a common random access memory. A feature of the SRAM lies in that as long as power is supplied to the SRAM, data stored in the SRAM will not be lost. This is different from a dynamic random access memory (DRAM) which has to periodically re-flash data lines. As a result, the SRAM still plays an irreplaceable role in today's electronic products.
The common SRAM has a so-called 6T structure comprising six transistors. Referring to FIG. 1, FIG. 1 shows a circuit diagram of a conventional 6T SRAM. FIG. 1 illustrates an SRAM 100 of size 1 bit. The SRAM 100 mainly comprises 4 transistors PL1, PD1, PL2, and PD2 which form a latched circuit to store data. Transistors PG1 and PG2 are respectively switches controlled by a word line WL. When the SRAM 100 is selected (to be written into or read from), the transistors PG1 and PG2 are turned on simultaneously and data is transmitted through a bit line BL and an inversion bit line BLB so as to perform data access. The SRAM 100 in FIG. 1 is merely a 1-bit memory unit, which, however, exists in a great quantity in one or a plurality of memory arrays having capacity of several million bits.
A so-called shmoo test is commonly used to test and analyze the SRAM. The shmoo test is often used for analysis of semiconductor circuits and generally for repetitively testing the operating voltage of the to-be-tested circuit having capacity of several million bits by gradually increasing or decreasing the operating voltage to evaluate the quality distribution of the to-be-tested circuit at various operating voltages. Referring simultaneously to both FIG. 1 and FIG. 2, FIG. 2 illustrates a distribution of the SRAM under the shmoo test. The horizontal axis in FIG. 2 represents a memory cell voltage VCell applied on the transistors PL1, PL2, PD1, and PD2 and the vertical axis represents a periphery voltage VPERI applied on the transistors PG1 and PG2. The stars in FIG. 2 represent the voltages at which all the SRAM in the circuit under test can work normally, while the blank areas represent the voltages at which not all the SRAM in the circuit under test can work normally.
In addition, a straight line 210 represents the situation when the memory cell voltage VCell is equal to the periphery voltage VPERI. A dot PT on the straight line 210 is where a minimal operating voltage Vcc_min of the SRAM under test occurs.
In general, the reasons why failure occurs in the SRAM include inevitable errors in the manufacturing process (generally referred to as early fail) in addition to two main factors, one being Static Noise Margin (SNM), and the other being Write Noise Margin (WMN). The latter two factors respectively represent noise tolerance of the SRAM when being read and written. Moreover, these two factors are usually inverse. That is, the SRAM having higher SNM usually has lower WNM and vice versa. As a result, when the SRAM needs to operate on a lower operating voltage, a designer has difficulty adjusting corresponding process parameters.
The abovementioned shmoo test can only indicate whether the failure of the SRAM under test is caused by the WNM or the SNM. Therefore, the shmoo test can not provide the designer enough information to properly adjust the process parameters of the SRAM corresponding to the SNM or the WNM and to further adjust the minimal operating voltage. Meanwhile, the shmoo test also can not provide information regarding whether there are early fail bits inherent therein.